The microelectronic industry is under intense pressure to produce high performance devices in small package sizes at continually decreasing costs. Smart phones, portable computers, digital cameras, portable music and media players, and many other electronic products require faster memory devices with more capacity. As such, memory device manufacturers in particular seek reliable, low-cost processes for fabricating high-performance devices.
Memory devices may have large arrays of memory cells, and reducing the size of individual memory cells provides a concomitant increase in the bit density of the memory devices. Cross-point memory cells are located in the vertical overlap regions between word lines and bit lines. Cross-point memory cells include structures that undergo a stable and detectable change when exposed to a current between a word line and a corresponding bit line. Because cross-point memory cells are located in the overlap regions between bit lines and word lines, these memory cells may theoretically be formed to extremely small dimensions.
One concern of manufacturing cross-point memory cells is that the smallest features of the structures can be difficult to form using photolithography processes. For example, it is difficult to pattern the wafers to form the drain structures of a cross-point memory cell because these features are so small that they cannot be formed reliably using existing photolithography processes. It is also difficult to photo-pattern gate structures that completely surround the individual pillars in high density cross-point memory arrays. Moreover, it is very expensive to form very small features using photolithography processes because these processes require expensive equipment and materials. Additional concerns of cross-point memory arrays include reversed leakage current, serial resistance, and accurate control of current-voltage uniformity that are important for multi-level cell configurations. Therefore, it is desired to develop improved methods for forming highly integrated circuitry, and in particular cross-point memory cells, and to develop improved circuitry for such features.